Present day digital memories, such as First-In First-Out devices (FIFOs) operate in response to a periodic clock signal generated by a system clock. With a FIFO device, the writing of data to successive locations occurs upon the receipt of successive write clock pulses. By the same token, the reading of data from each of the successive locations previously written with data occurs upon the receipt of successive read clock pulses. Dynamic phase and frequency differences between the read and write clock create jitter. Increasing the read clock frequency will reduce the incidence of jitter. However, in a device such as a FIFO, increasing the read clock frequency can lead to reading the device too rapidly without a corresponding increase in the write clock frequency. Increasing the write clock frequency will overcome this difficulty. However, the ability to increase the write clock frequency does not always exist.
Thus, there is a need for a technique for accessing data written into a memory device that overcomes the aforementioned disadvantages.